Self-aligned isolation dielectric structures for a three-dimensional memory device
US9859363B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2016 |
| Grant date | Jan 2, 2018 |
| Priority date | — |
| Expiry date | May 16, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/84
Abstract
A method of dividing drain select gate electrodes in a three-dimensional vertical memory device is provided. An alternating stack of insulating layers and spacer material layers is formed over a substrate. A first insulating cap layer is formed over the alternating stack. A plurality of memory stack structures is formed through the alternating stack and the first insulating cap layer. The first insulating cap layer is vertically recessed, and a conformal material layer is formed over protruding portions of the memory stack structures. Spacer portions are formed by an anisotropic etch of the conformal material layer such that the sidewalls of the spacer portions having protruding portions. A self-aligned separator trench with non-uniform sidewalls having protruding portions is formed through an upper portion of the alternating stack by etching the upper portions of the alternating stack between the spacer portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.