Nanoscale structure with epitaxial film having a recessed bottom portion

US9865684B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Benjamin Chu-Kung · Portland, US
• Van H. Le · Portland, US
• Robert S. Chau · Beaverton, US
• Sansaptak Dasgupta · Hillsboro, US
• Gilbert Dewey · Beaverton, US
• Niti Goel · Portland, US
• Jack T. Kavalieros · Portland, US
• Matthew V. Metz · Portland, US
• Niloy Mukherjee · Beaverton, US
• Ravi Pillarisetty · Portland, US
• Willy Rachmady · Beaverton, US
• Marko Radosavljevic · Portland, US
• Han Wui Then · Portland, US
• Nancy Zelick · Portland, US

Key dates

• Filing date: May 8, 2015
• Grant date: Jan 9, 2018
• Expiry date: Oct 3, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/3086
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An embodiment of the invention includes an epitaxial layer that directly contacts, for example, a nanowire, fin, or pillar in a manner that allows the layer to relax with two or three degrees of freedom. The epitaxial layer may be included in a channel region of a transistor. The nanowire, fin, or pillar may be removed to provide greater access to the epitaxial layer. Doing so may allow for a “all-around gate” structure where the gate surrounds the top, bottom, and sidewalls of the epitaxial layer. Other embodiments are described herein.