Conductivity improvements for III-V semiconductor devices

US9899505B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Marko Radosavljevic · Portland, US
• Prashant Majhi · San Jose, US
• Jack T. Kavalieros · Portland, US
• Niti Goel · Portland, US
• Wilman Tsai · Saratoga, US
• Niloy Mukherjee · Beaverton, US
• Yong Ju Lee · Daejeon, KR
• Gilbert Dewey · Beaverton, US
• Willy Rachmady · Beaverton, US

Key dates

• Filing date: Jan 14, 2015
• Grant date: Feb 20, 2018
• Expiry date: Jan 14, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.