Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors
US9905643B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2016 |
| Grant date | Feb 27, 2018 |
| Priority date | — |
| Expiry date | Aug 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A nano-sheet semiconductor structure and a method for fabricating the same. The nano-sheet structure includes a substrate and at least one alternating stack of semiconductor material layers and metal gate material layers. The nano-sheet semiconductor structure further comprises a source region and a drain region. A first plurality of epitaxially grown interconnects contacts the source region and the semiconductor layers in the alternating stack. A second plurality of epitaxially grown interconnects contacts the drain region and the semiconductor layers in the alternating stack. The method includes removing a portion of alternating semiconductor layers and metal gate material layers. A first plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the source region. A second plurality of interconnects is epitaxially grown between and in contact with the semiconductor layers and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.