Sean Teehan
70Patents
8h-index
24Co-inventors
70Inventor score
Filing activity: Jun 18, 2014 → Apr 12, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9608065B1 | Air gap spacer for metal gates | Electricity | 89 | Active |
| US9620590B1 | Nanosheet channel-to-source and drain isolation | Electricity | 86 | Active |
| US9362179B1 | Method to form dual channel semiconductor material fins | Electricity | 24 | Active |
| US9905643B1 | Vertically aligned nanowire channels with source/drain interconnects for nanosheet transistors | Electricity | 22 | Active |
| US9450095B1 | Single spacer for complementary metal oxide semiconductor process flow | Electricity | 13 | Active |
| US9318574B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 11 | Active |
| US10074730B2 | Forming stacked nanowire semiconductor device | Electricity | 8 | Active |
| US10014391B2 | Vertical transport field effect transistor with precise gate length definition | Electricity | 8 | Active |
| US9728622B1 | Dummy gate formation using spacer pull down hardmask | Electricity | 7 | Active |
| US10211055B2 | Fin patterns with varying spacing without fin cut | Electricity | 7 | Active |
| US9842739B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 6 | Active |
| US9659779B2 | Method and structure for enabling high aspect ratio sacrificial gates | Electricity | 5 | Active |
| US10043801B2 | Air gap spacer for metal gates | Electricity | 4 | Active |
| US10249738B2 | Nanosheet channel-to-source and drain isolation | Electricity | 4 | Active |
| US9536744B1 | Enabling large feature alignment marks with sidewall image transfer patterning | Electricity | 4 | Active |
| US10381437B2 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US9917196B1 | Semiconductor device and method of forming the semiconductor device | Electricity | 4 | Active |
| US9893166B2 | Dummy gate formation using spacer pull down hardmask | Electricity | 3 | Active |
| US10833190B2 | Super long channel device within VFET architecture | Electricity | 3 | Active |
| US9786666B2 | Method to form dual channel semiconductor material fins | Electricity | 3 | Active |
| US10615269B2 | Nanosheet channel-to-source and drain isolation | Electricity | 3 | Active |
| US9953915B2 | Electrically conductive interconnect including via having increased contact surface area | Electricity | 2 | Active |
| US9553044B2 | Electrically conductive interconnect including via having increased contact surface area | Electricity | 2 | Active |
| US9991117B2 | Fin patterns with varying spacing without fin cut | Electricity | 2 | Active |
| US11043581B2 | Nanosheet channel-to-source and drain isolation | Electricity | 2 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.