Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs

US9911835B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Roza Kotlyar · Portland, US
• Stephen M. Cea · Hillsboro, US
• Gilbert Dewey · Beaverton, US
• Benjamin Chu-Kung · Portland, US
• Uygar E. Avci · Portland, US
• Rafael Rios · Portland, US
• Anurag Chaudhry · Portland, US
• Thomas D. Linton · Lake Saint Louis, US
• Ian A. Young · Portland, US
• Kelin J. Kuhn · Beaverton, US

Key dates

• Filing date: Jan 19, 2017
• Grant date: Mar 6, 2018
• Expiry date: Jan 19, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/85

Abstract

Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.