Memory first process flow and device
US9917166B2 · kind B2 · utility
3Cited by
19References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 13, 2016 |
| Grant date | Mar 13, 2018 |
| Priority date | — |
| Expiry date | Jun 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
Abstract
A semiconductor device includes a substrate comprising a source region and a drain region, a bit storing element formed on the substrate, a memory gate structure, a first insulating layer formed on the substrate, a second insulating layer formed on the substrate, and a select gate structure formed on the first insulating layer. The second insulating layer is formed on the memory gate structure and the select gate structure and between the memory gate structure and the select gate structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.