Gate contact with vertical isolation from source-drain
US9935168B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 28, 2017 |
| Grant date | Apr 3, 2018 |
| Priority date | — |
| Expiry date | Feb 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0275
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor structure includes forming a gate structure having a first conductive material above a semiconductor substrate, gate spacers on opposing sides of the first conductive material, and a first interlevel dielectric (ILD) layer surrounding the gate spacers and the first conductive material. An upper portion of the first conductive material is recessed. The gate spacers are recessed until a height of the gate spacers is less than a height of the gate structure. An isolation liner is deposited above the gate spacers and the first conductive material. A portion of the isolation liner is removed so that a top surface of the first conductive material is exposed. A second conductive material is deposited in a contact hole created above the first conductive material and the gate spacers to form a gate contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.