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US9946676B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Mahesh Wagh · Portland, US
• Zuoguo Wu · San Jose, US
• Venkatraman Iyer · Austin, US
• Gerald Pasdast · San Jose, US
• Mark S. Birrittella · Chippewa Falls, US
• Ishwar Agarwal · Redmond, US
• Lip Khoon Teh · Air Itam, MY
• Su Wei Lim · Klang, MY
• Anoop Kumar Upadhyay · Sidhauli, IN

Key dates

• Filing date: Mar 26, 2015
• Grant date: Apr 17, 2018
• Expiry date: Nov 13, 2035

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/4068
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system-on-a-chip, such as a logical PHY, may be divided into hard IP blocks with fixed routing, and soft IP blocks with flexible routing. Each hard IP block may provide a fixed number of lanes. Using p hard IP blocks, where each block provides n data lanes, h=n*p total hard IP data lanes are provided. Where the system design calls for k total data lanes, it is possible that k≠h, so that ┌k/n┐ hard IP blocks provide h=n*p available hard IP data lanes. In that case, h−k lanes may be disabled. In cases where lane reversals occur, such as between hard IP and soft IP, bowtie routing may be avoided by the use of a multiplexer-like programmable switch within the soft IP.