Methods of forming gate electrodes on a vertical transistor device
US9966456B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 8, 2016 |
| Grant date | May 8, 2018 |
| Priority date | — |
| Expiry date | Nov 26, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0172
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method of forming a vertical transistor device disclosed herein includes, among other things, forming bottom source/drain (S/D) regions. A plurality of vertically oriented channel semiconductor structures is formed above the bottom source/drain (S/D) regions. A gate insulation layer is formed above the vertically oriented channel semiconductor structures. A conformal layer of conductive gate material is formed above the gate insulation layer. The conformal layer of conductive material is etched to define conductive gate spacers on sidewalls of the vertically oriented channel semiconductor structures. Top source/drain (S/D) regions are formed above the vertically oriented channel semiconductor structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.