Margin for fin cut using self-aligned triple patterning
US9997369B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2016 |
| Grant date | Jun 12, 2018 |
| Priority date | — |
| Expiry date | Sep 27, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0337
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor structure. The method includes forming a plurality of mandrel structures. A plurality of first spacers is formed on sidewalls of the mandrel structures. A plurality of second spacers is formed on sidewalls of the first spacers. The plurality of first spacers is removed selective to the plurality of second spacers and mandrel structures. A cut mask is formed over a first set of second spacers in the plurality of second spacers and a first set of mandrel structures in the plurality of mandrel structures. A second set of second spacers in the plurality of spacers and a second set of mandrel structures in the plurality of mandrel structures remain exposed. One of the second set of mandrel structures and the second set of second spacers is removed selective to the second set of second spacers and the second set of mandrel structures, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.