De-Yang Chiou
9Patents
1h-index
23Co-inventors
40Inventor score
Filing activity: Oct 5, 2020 → Jan 24, 2024
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US11916022B2 | Photolithography alignment process for bonded wafers | Electricity | 1 | Active |
| US11942447B2 | Storage layers for wafer bonding | Electricity | 0 | Active |
| US11362038B2 | Photolithography alignment process for bonded wafers | Electricity | 0 | Active |
| US12315837B2 | Storage layers for wafer bonding | Electricity | 0 | Active |
| US12360314B2 | Photonic semiconductor-on-insulator (SOI) substrate and method for forming the photonic SOI substrate | Physics | 0 | Active |
| US11942358B2 | Low thermal budget dielectric for semiconductor devices | Electricity | 0 | Active |
| US12347717B2 | Debonding structures for wafer bonding | Electricity | 0 | Active |
| US12341056B2 | Method of fabricating a semiconductor structure and semiconductor structure obtained therefrom | Electricity | 0 | Active |
| US12230585B2 | Photolithography alignment process for bonded wafers | Electricity | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.