Vertical transport field effect transistor with precise gate length definition
US10014391B2 · kind B2 · utility
8Cited by
11References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2016 |
| Grant date | Jul 3, 2018 |
| Priority date | — |
| Expiry date | Jun 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques relate to a gate stack for a semiconductor device. A vertical fin is formed on a substrate. The vertical fin has an upper portion and a bottom portion. The upper portion of the vertical fin has a recessed portion on sides of the upper portion. A gate stack is formed in the recessed portion of the upper portion of the vertical fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.