Patent · US Active

Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon-germanium region

US10038075B2 · kind B2 · utility

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Key dates

Filing dateFeb 21, 2017
Grant dateJul 31, 2018
Priority date
Expiry dateFeb 21, 2037

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/01

Abstract

An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.