Forming stacked nanowire semiconductor device
US10074730B2 · kind B2 · utility
8Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 2016 |
| Grant date | Sep 11, 2018 |
| Priority date | — |
| Expiry date | Jan 28, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6219
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.