Recessed high voltage metal oxide semiconductor transistor for RRAM cell
US10115819B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2015 |
| Grant date | Oct 30, 2018 |
| Priority date | — |
| Expiry date | May 29, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
Abstract
A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.