Integrated structures including material containing silicon, nitrogen, and at least one of carbon, oxygen, boron and phosphorus

US10157933B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Justin B. Dorhout · Boise, US
• Fei Wang · Beijing, CN
• Chet E. Carter · Boise, US
• Ian C. Laboriante · Boise, US
• John D. Hopkins · Meridian, US
• Kunal Shrotri · Boise, US
• Ryan Meyer · Boise, US
• Vinayak Shamanna · Boise, US
• Kunal R. Parekh · Boise, US
• Martin C. Roberts · Boise, US
• Matthew Park · Boise, US

Key dates

• Filing date: Apr 19, 2016
• Grant date: Dec 18, 2018
• Expiry date: Apr 19, 2036

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/35
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. A layer over the conductive levels includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus. In some embodiments the vertically-stacked conductive levels are wordline levels within a NAND memory array. Some embodiments include an integrated structure having vertically-stacked conductive levels alternating with dielectric levels. Vertically-stacked NAND memory cells are along the conductive levels within a memory array region. A staircase region is proximate the memory array region. The staircase region has electrical contacts in one-to-one correspondence with the conductive levels. A layer is over the memory array region and over the staircase region. The layer includes silicon, nitrogen, and one or more of carbon, oxygen, boron and phosphorus.