Silicon-on-nothing transistor semiconductor structure with channel epitaxial silicon region
US10170475B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Mar 3, 2017 |
| Grant date | Jan 1, 2019 |
| Priority date | — |
| Expiry date | Mar 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/201
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An improved transistor with channel epitaxial silicon. In one aspect, a method of fabrication includes: forming a gate stack structure on an epitaxial silicon region disposed on a substrate, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; and growing a raised epitaxial source and drain from the substrate, the raised epitaxial source and drain in contact with the epitaxial silicon region and the gate stack structure. For a SRAM device, further: removing an epitaxial layer in contact with the silicon substrate and the raised source and drain and to which the epitaxial silicon region is coupled leaving a space above the silicon substrate and under the raised epitaxial source and drain; and filling the space with an insulating layer and isolating the raised epitaxial source and drain and a channel of the transistor from the silicon substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.