Subtractive etch interconnects
US10177031B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 23, 2014 |
| Grant date | Jan 8, 2019 |
| Priority date | — |
| Expiry date | Aug 7, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an integrated metal line and interconnect. The method may include forming a first trench in a first ILD exposing a lower metal line, the first ILD is above a substrate, and the lower metal line is in the substrate; forming a first barrier layer in the first trench; forming an integrated metal layer (including a first metal line and a first via) on the first barrier layer; forming a first hardmask on the integrated metal layer; forming an isolation trench in the first hardmask and in the first metal line; forming a second barrier layer in the isolation trench; removing a portion of the second barrier layer from a bottom of the isolation trench exposing the first ILD; and forming a second ILD on the second barrier and in the isolation trench, where a bottom of the second ILD is in the first ILD.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.