Devices with chamfer-less vias multi-patterning and methods for forming chamfer-less vias
US10181420B2 · kind B2 · utility
2Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 6, 2017 |
| Grant date | Jan 15, 2019 |
| Priority date | — |
| Expiry date | Feb 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.