Method of forming complementary nano-sheet/wire transistor devices with same depth contacts
US10304833B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 2018 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Feb 19, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A device includes a first nano-sheet of a first semiconductor material. First source/drain regions are positioned adjacent ends of the first nano-sheet. A first dielectric material is positioned above the first source/drain regions. A second nano-sheet of a second semiconductor material is positioned above the first nano-sheet. Second source/drain regions are positioned adjacent ends of the second nano-sheet and above the first dielectric material. A gate structure has a first portion capacitively coupled to the first nano-sheet and a second portion capacitively coupled to the second nano-sheet. A first source/drain contact contacts a first portion of the second source/drain regions in a first region where the first and second source/drain regions do not vertically overlap. The first source/drain contact has a first depth that extends below a height of an upper surface of the first source/drain regions in a second region where the first and second source/drain regions vertically overlap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.