FDSOI semiconductor device with contact enhancement layer and method of manufacturing

US10347543B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Peter Baars · Dresden, DE
• Rick Carter · Saratoga Springs, US
• Vikrant Chauhan · Beacon, US
• George Jonathan Kluth · Sunnyvale, US
• Anurag Mittal · Saratoga Springs, US
• David Pritchard · Beacon, US
• Mahbub Rashed · Cupertino, US

Key dates

• Filing date: Nov 13, 2017
• Grant date: Jul 9, 2019
• Expiry date: Nov 13, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of forming contacts includes forming a plurality of transistor devices separated by shallow trench insulator regions, the transistor devices each comprising a semiconductor substrate, a buried insulator layer on the semiconductor bulk substrate, a semiconductor layer on the buried insulator layer, a high-k metal gate stack on the semiconductor layer and a gate electrode above the high-k metal gate stack, raised source/drain regions on the semiconductor layer, and a silicide contact layer above the raised source/drain regions and the gate electrode, providing an interlayer dielectric stack on the silicide contact layer and planarizing the interlayer dielectric stack, patterning a plurality of contacts through the interlayer dielectric stack onto the raised source/drain regions, and, for at least some of the contacts, patterning laterally extended contact regions above the contacts, the laterally extended contact regions extending over shallow trench insulator regions neighboring the corresponding raised source/drain regions.