Methods of forming source/drain contact structures on integrated circuit products

US10373877B1 · kind B1 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Haiting Wang · Clifton Park, US
• Hong Yu · Rexford, US
• Hui Zang · Guilderland, US
• Wei Zhao · Zhuhai, CN
• Yue Zhong · Ballston Lake, US
• Guowei Xu · Lawrence, US
• Laertis Economikos · Hopewell Junction, US
• Jerome Ciavatti · Mechanicville, US
• Scott Beasor · Greenwich, US

Key dates

• Filing date: May 22, 2018
• Grant date: Aug 6, 2019
• Expiry date: May 22, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/215
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

One illustrative method disclosed herein includes forming a plurality of transistors on a semiconductor substrate, wherein each of the transistors comprise source/drain epitaxial semiconductor material in the source/drain regions, a contact etch stop layer (CESL) positioned above the source/drain epitaxial semiconductor material and an insulating material positioned above the contact etch stop layer, and forming a plurality of contact isolation cavities by performing at least one etching process sequence, wherein the etching process sequence is adapted to sequentially remove the insulating material, the CESL and the source/drain epitaxial semiconductor material, and forming a contact isolation structure in each of the contact isolation cavities. In this example, the method also includes, after forming the contact isolation structures, removing the sacrificial gate structures so as to form a plurality of replacement gate cavities, and forming a final gate structure in each of the plurality of replacement gate cavities.