Field-effect transistors with fins formed by a damascene-like process
US10403742B2 · kind B2 · utility
1Cited by
5References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2017 |
| Grant date | Sep 3, 2019 |
| Priority date | — |
| Expiry date | Sep 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming a structure for a fin-type field-effect transistor and structures for a fin-type field-effect transistor. An etch stop layer, a sacrificial layer, and a dielectric layer are arranged in a layer stack formed on a substrate. a plurality of openings are formed that extend through the layer stack to the substrate. A semiconductor material is epitaxially grown inside each of the plurality of openings from the substrate to form a plurality of fins embedded in the layer stack. The sacrificial layer is removed selective to the etch stop layer to reveal a section of each of the plurality of fins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.