Instructions and logic to perform floating-point and integer operations for machine learning

US10474458B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Himanshu Kaul · Portland, US
• Mark A. Anders · Hillsboro, US
• Sanu K. Mathew · Hillsboro, US
• Anbang Yao · Beijing, CN
• Joydeep Ray · Folsom, US
• Ping T. Tang · Edison, US
• Michael S. Strickland · Sunnyvale, US
• Xiaoming Chen · Xi'an, CN
• Tatiana Shpeisman · Menlo Park, US
• Abhishek R. Appu · Cameron Park, US
• Altug Koker · Cameron Park, US
• Kamal Sinha · Rancho Cordova, US
• Balaji Vembu · Folsom, US
• Nicolas C. Galoppo Von Borries · Portland, US
• Eriko Nurvitadhi · Beaverton, US
• Rajkishore Barik · Santa Clara, US
• Tsung-Han Lin · Campbell, US
• Vasanth Ranganathan · Cameron Park, US
• Sanjeev Jahagirdar · Folsom, US

Key dates

• Filing date: Oct 18, 2017
• Grant date: Nov 12, 2019
• Expiry date: Oct 18, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06T15/005
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

One embodiment provides for a machine-learning hardware accelerator comprising a compute unit having an adder and a multiplier that are shared between integer data path and a floating-point datapath, the upper bits of input operands to the multiplier to be gated during floating-point operation.