Scaled memory structures or other logic devices with middle of the line cuts

US10475890B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Haiting Wang · Clifton Park, US
• Wei Zhao · Zhuhai, CN
• Hui Zang · Guilderland, US
• Hong Yu · Rexford, US
• Zhenyu Hu · Leonberg, DE
• Scott Beasor · Greenwich, US
• Erik Geiss · Wappingers Falls, US
• Jerome Ciavatti · Mechanicville, US
• Jae Gon Lee · Singapore, SG

Key dates

• Filing date: Oct 9, 2017
• Grant date: Nov 12, 2019
• Expiry date: Oct 27, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/853

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to scaled memory structures with middle of the line cuts and methods of manufacture The structure comprises: a plurality of fin structures formed on a substrate; a plurality of gate structures spanning over adjacent fin structures; a cut in adjacent epitaxial source/drain regions; and a cut in contact material formed adjacent to the plurality of gate structures, which provides separate contacts.