Patent · US Active

Sector cache for compression

US10503652B2 · kind B2 · utility

0Cited by

3References

18Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Abhishek R. Appu · Cameron Park, US
Altug Koker · Cameron Park, US
Joydeep Ray · Folsom, US
David Puffer · Tempe, US
Prasoonkumar Surti · Folsom, US
Lakshminarayanan Striramassarma · Folsom, US
Vasanth Ranganathan · Cameron Park, US
Kiran C. Veernapu · Kanchinakote, IN
Balaji Vembu · Folsom, US
Pattabhiraman K · Bengaluru, IN

Key dates

Filing date	Apr 1, 2017
Grant date	Dec 10, 2019
Priority date	—
Expiry date	Apr 20, 2037

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.