Stacked die semiconductor package with electrical interposer

US10629575B1 · kind B1 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Thorsten Scharf · Regensburg, DE
• Carsten Ahrens · Birkenfeld, DE
• Helmut Brech · Lappersdorf, DE
• Martin Gruber · Schwandorf, DE
• Thorsten Meyer · Regensburg, DE
• Matthias Zigldrum · Regensburg, DE

Key dates

• Filing date: Dec 13, 2018
• Grant date: Apr 21, 2020
• Expiry date: Dec 13, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3511
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor chip assembly includes first and second semiconductor dies that each include opposite facing upper and lower sides and an outer edge side, and an electrical interposer having opposite facing first and second conductive surfaces and a conductive connection between the conductive surfaces. The second semiconductor die is mounted on top of the first semiconductor die and the interposer such that the lower side of the second semiconductor die faces the first semiconductor die and the interposer, a first lateral section of the second semiconductor die at least partially covers the upper side of the first semiconductor die, and a second lateral section of the second semiconductor die extends past the outer edge side of the first semiconductor die. The first conductive surface is electrically connected to a first terminal that is disposed on a lower side of the second semiconductor die.