Methods of forming spacers adjacent gate structures of a transistor device
US10629739B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2018 |
| Grant date | Apr 21, 2020 |
| Priority date | — |
| Expiry date | Jul 18, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/121
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One illustrative method disclosed herein includes forming a low-k sidewall spacer adjacent opposing sidewalls of a gate structure, forming contact etch stop layers (CESLs) adjacent the low-k sidewall spacer in the source/drain regions of the transistor, and forming a first insulating material above the CESLs. In this example, the method also includes recessing the first insulating material so as to expose substantially vertically oriented portions of the CESLs, removing a portion of a lateral width of the substantially vertically oriented portions of the CESLs so as to form trimmed CESLs, and forming a high-k spacer on opposite sides of the gate structure, wherein at least a portion of the high-k spacer is positioned laterally adjacent the trimmed substantially vertically oriented portions of the trimmed CESLs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.