Binary, ternary and bit serial compute-in-memory circuits

US10642922B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Phil Knag · Portland, US
• Gregory K. Chen · Ann Arbor, US
• Raghavan Kumar · Hillsboro, US
• Huseyin Ekin Sumbul · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Sasikanth Manipatruni · Ithaca, US
• Amrita Mathuriya · Portland, US
• Ram Krishnamurthy · Portland, US
• Ian A. Young · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: May 5, 2020
• Expiry date: Sep 28, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/56
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.