Through array contact (TAC) for three-dimensional memory devices
US10658378B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2018 |
| Grant date | May 19, 2020 |
| Priority date | — |
| Expiry date | Jul 27, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of interconnect structures of a three-dimensional (3D) memory device and method for forming the interconnect structures are disclosed. In an example, a 3D NAND memory device includes a semiconductor substrate, an alternating layer stack disposed on the semiconductor substrate, and a dielectric structure, which extends vertically through the alternating layer stack, on an isolation region of the substrate. Further, the alternating layer stack abuts a sidewall surface of the dielectric structure and the dielectric structure is formed of a dielectric material. The 3D memory device additionally includes one or more through array contacts that extend vertically through the dielectric structure and the isolation region, and one or more channel structures that extend vertically through the alternating layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.