Staircase structure for memory device
US10680003B2 · kind B2 · utility
4Cited by
9References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 10, 2018 |
| Grant date | Jun 9, 2020 |
| Priority date | — |
| Expiry date | Sep 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure disposed over a substrate. The staircase structure includes a plurality of layer stacks, where each layer stack is made of a first material layer over a portion of a second material layer. The staircase structure further includes a plurality of landing pads, where each landing pad is disposed over another portion of the second material layer of a respective layer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.