Self-aligned cuts in an interconnect structure
US10685874B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2018 |
| Grant date | Jun 16, 2020 |
| Priority date | — |
| Expiry date | Dec 14, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76897
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for forming a cut between interconnects and structures with cuts between interconnects. A layer is patterned to form first, second, and third features having a substantially parallel alignment with the second feature between the first feature and the third feature. A sacrificial layer is formed that is arranged between the first and second features and between the second and third features. The sacrificial layer is patterned to form a cut between the first and second features from which a portion of the sacrificial layer is fully removed and to form a cavity in a portion of the sacrificial layer between the second and third features. A dielectric layer is formed inside the cut between the first and second features. After depositing the section of the dielectric material and forming the dielectric layer, the sacrificial layer is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.