Transistor with recessed cross couple for gate contact over active region integration

US10770388B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Ruilong Xie · Niskayuna, US
• Veeraraghavan S. Basker · Schenectady, US
• Kangguo Cheng · Schenectady, US
• Jia Zeng · Nanhu, CN
• Youngtag Woo · San Ramon, US
• Mahender Kumar · Hopewell Junction, US
• Guillaume Bouche · Albany, US

Key dates

• Filing date: Jun 15, 2018
• Grant date: Sep 8, 2020
• Expiry date: Jun 15, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B10/12
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor structure includes a substrate having a first region and a second region, a first source/drain disposed on the substrate in the first region, an interlevel dielectric (ILD) disposed on the source/drain, and a first gate disposed on the substrate. The semiconductor structure further includes a first contact trench within the ILD extending to the first source/drain, a first trench contact within the first contact trench, and a first source/drain contact trench extending to the first trench contact. The semiconductor structure further includes a cross couple contact trench within the ILD, and a cross couple contact disposed in the cross couple contact trench in contact with the first gate and the first trench contact. The cross couple contact couples the first source/drain and the first gate.