Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions

US10818751B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Mona A. Ebrish · Albany, US
• Fee Li Lie · Albany, US
• Nicolas Loubet · Guilderland, US
• Gauri Karve · Cohoes, US
• Indira Seshadri · Niskayuna, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Leigh Anne H. Clevenger · Rhinebeck, US

Key dates

• Filing date: Mar 1, 2019
• Grant date: Oct 27, 2020
• Expiry date: Mar 1, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/013
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.