Binary, ternary and bit serial compute-in-memory circuits
US10860682B2 · kind B2 · utility
8Cited by
1References
19Claims
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Key dates
| Filing date | Apr 2, 2020 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Apr 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/56
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary CIM circuit enables all memory cells in a memory array to be effectively accessible simultaneously for computation using fixed pulse widths on the wordlines and equal capacitance on the bitlines. The fixed pulse widths and equal capacitance ensure that a minimum voltage drop in the bitline represents one least significant bit (LSB) so that the bitline voltage swing remains safely within the maximum allowable range. The binary CIM circuit maximizes the effective memory bandwidth of a memory array for a given maximum voltage range of bitline voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.