Three-dimensional memory devices
US10867678B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2018 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices are disclosed. In an example, a 3D memory device includes a substrate, a peripheral device disposed on the substrate, a memory stack disposed above the peripheral device and including a plurality of conductor/dielectric layer pairs, and a plurality of memory strings. Each of the memory strings extends vertically through the memory stack and includes a drain select gate and a source select gate above the drain select gate. Edges of the conductor/dielectric layer pairs in a staircase structure of the memory stack along a vertical direction away from the substrate are staggered laterally toward the memory strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.