Spacer structures for a transistor device

US10872979B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Hui Zang · Guilderland, US
• Chung Foong Tan · Singapore, SG
• Guowei Xu · Lawrence, US
• Haiting Wang · Clifton Park, US
• Yue Zhong · Ballston Lake, US
• Ruilong Xie · Niskayuna, US
• Tek Po Rinus Lee · Malta, US
• Scott Beasor · Greenwich, US

Key dates

• Filing date: Jan 30, 2020
• Grant date: Dec 22, 2020
• Expiry date: Jan 30, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/121
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.