Three-dimensional memory devices and fabricating methods thereof
US10892274B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Oct 17, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
Abstract
Embodiments of 3D memory devices and fabricating methods are disclosed. The method can comprise: forming an alternating dielectric stack on a substrate; forming a channel hole penetrating the alternating dielectric stack to expose a surface of the substrate; forming an epitaxial layer on a bottom of the channel hole; forming a functional layer covering a sidewall of the channel hole and a top surface of the epitaxial layer; forming a protecting layer covering the functional layer; removing portions of the functional layer and the protecting layer to form an opening to expose a surface of the epitaxial layer; expanding the opening laterally to increase an exposed area of the epitaxial layer at the bottom of the channel hole; and forming a channel structure on the sidewall of the channel hole and being in electrical contact with the epitaxial layer through the expanded opening.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.