Low power ferroelectric based majority logic gate adder
US10944404B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/694
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An adder uses with first and second majority gates. For a 1-bit adder, output from a 3-input majority gate is inverted and input two times to a 5-input majority gate. Other inputs to the 5-input majority gate are the same as those of the 3-input majority gate. The output of the 5-input majority gate is a sum while the output of the 3-input majority gate is the carry. Multiple 1-bit adders are concatenated to form an N-bit adder. The input signals to the majority gates can be analog, digital, or a combination of them, which are driven to first terminals of non-ferroelectric capacitors. The second terminals of the non-ferroelectric capacitors are coupled to form a majority node. Majority function of the input signals occurs on this node. The majority node is then coupled to a first terminal of a non-linear polar capacitor. The second terminal of the capacitor provides the output of the logic gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.