Compute-in-memory circuit having a multi-level read wire with isolated voltage distributions

US10956813B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ian A. Young · Portland, US
• Ram Krishnamurthy · Portland, US
• Sasikanth Manipatruni · Ithaca, US
• Gregory K. Chen · Ann Arbor, US
• Amrita Mathuriya · Portland, US
• Abhishek A. Sharma · Hillsboro, US
• Raghavan Kumar · Hillsboro, US
• Phil Knag · Portland, US
• Huseyin Ekin Sumbul · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Mar 23, 2021
• Expiry date: Jan 6, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H03M7/6011
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus is described. The apparatus includes a compute in memory circuit. The compute in memory circuit includes a memory circuit and an encoder. The memory circuit is to provide 2m voltage levels on a read data line where m is greater than 1. The memory circuit includes storage cells sufficient to store a number of bits n where n is greater than m. The encoder is to receive an m bit input and convert the m bit input into an n bit word that is to be stored in the memory circuit, where, the m bit to n bit encoding performed by the encoder creates greater separation between those of the voltage levels that demonstrate wider voltage distributions on the read data line than others of the voltage levels.