Compute in memory circuits with multi-Vdd arrays and/or analog multipliers

US11061646B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Huseyin Ekin Sumbul · Portland, US
• Phil Knag · Portland, US
• Gregory K. Chen · Ann Arbor, US
• Raghavan Kumar · Hillsboro, US
• Abhishek A. Sharma · Hillsboro, US
• Sasikanth Manipatruni · Ithaca, US
• Amrita Mathuriya · Portland, US
• Ram Krishnamurthy · Portland, US
• Ian A. Young · Portland, US

Key dates

• Filing date: Sep 28, 2018
• Grant date: Jul 13, 2021
• Expiry date: Aug 31, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/419
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Compute-in memory circuits and techniques are described. In one example, a memory device includes an array of memory cells, the array including multiple sub-arrays. Each of the sub-arrays receives a different voltage. The memory device also includes capacitors coupled with conductive access lines of each of the multiple sub-arrays and circuitry coupled with the capacitors, to share charge between the capacitors in response to a signal. In one example, computing device, such as a machine learning accelerator, includes a first memory array and a second memory array. The computing device also includes an analog processor circuit coupled with the first and second memory arrays to receive first analog input voltages from the first memory array and second analog input voltages from the second memory array and perform one or more operations on the first and second analog input voltages, and output an analog output voltage.