Programmable interface to in-memory cache processor

US11151046B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Amrita Mathuriya · Portland, US
• Sasikanth Manipatruni · Ithaca, US
• Victor W. Lee · Santa Clara, US
• Huseyin Ekin Sumbul · Portland, US
• Gregory K. Chen · Ann Arbor, US
• Raghavan Kumar · Hillsboro, US
• Phil Knag · Portland, US
• Ram Krishnamurthy · Portland, US
• Ian A. Young · Portland, US
• Abhishek A. Sharma · Hillsboro, US

Key dates

• Filing date: Jul 6, 2020
• Grant date: Oct 19, 2021
• Expiry date: Jul 6, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/251
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

The present disclosure is directed to systems and methods of implementing a neural network using in-memory mathematical operations performed by pipelined SRAM architecture (PISA) circuitry disposed in on-chip processor memory circuitry. A high-level compiler may be provided to compile data representative of a multi-layer neural network model and one or more neural network data inputs from a first high-level programming language to an intermediate domain-specific language (DSL). A low-level compiler may be provided to compile the representative data from the intermediate DSL to multiple instruction sets in accordance with an instruction set architecture (ISA), such that each of the multiple instruction sets corresponds to a single respective layer of the multi-layer neural network model. Each of the multiple instruction sets may be assigned to a respective SRAM array of the PISA circuitry for in-memory execution. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of in-memory vector/tensor calculations in furtherance of neural network processing without burdening the processor circuitry.