Barrier-less prefilled via formation
US11152257B2 · kind B2 · utility
2Cited by
5References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 16, 2020 |
| Grant date | Oct 19, 2021 |
| Priority date | — |
| Expiry date | Jan 16, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53209
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a semiconductor device includes forming one or more layers including at least one of a liner and a barrier along surfaces of a first interlevel dielectric (ILD) layer within a trench, after forming the one or more liners, performing a via etch to form a via opening exposing a first conductive line corresponding to a first metallization level, and forming, within the via opening and on the first conductive line, a barrier-less prefilled via including first conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.