Process integration approach for selective metal via fill
US11164780B2 · kind B2 · utility
1Cited by
13References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2019 |
| Grant date | Nov 2, 2021 |
| Priority date | — |
| Expiry date | Jul 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76843
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus for an interconnect formed on a substrate and a method of forming the interconnect thereon. In embodiments, the methods include etching through a hard mask disposed atop a low-k dielectric layer to form a via through the low-k dielectric layer and expose a conductive surface; contacting the conductive surface with dilute hydrofluoric acid to remove contaminants therefrom; removing the hard mask disposed atop the low-k dielectric layer; and applying a remote hydrogen plasma to the conductive surface to form an exposed portion of the conductive surface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.