Top via with next level line selective growth
US11171084B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 2020 |
| Grant date | Nov 9, 2021 |
| Priority date | — |
| Expiry date | Apr 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/7688
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.