Top via interconnect having a line with a reduced bottom dimension
US11189568B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 29, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Apr 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1063
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.