VTFET with cell height constraints
US11189725B2 · kind B2 · utility
1Cited by
6References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Nov 30, 2021 |
| Priority date | — |
| Expiry date | Jan 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
Abstract
Semiconductor devices and methods of forming the same include forming a restraint structure over a channel fin, having an opening that is smaller than a top surface of the channel fin. A top semiconductor structure is grown from the top surface of the channel fin, with lateral growth of the semiconductor structure being limited by the restraint structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.