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US11195792B2 · kind B2 · utility

1Cited by
23References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 10, 2020
Grant dateDec 7, 2021
Priority date
Expiry dateFeb 1, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L23/53257
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure includes a first metallization layer disposed on a first etch stop layer. The first metallization layer includes a first conductive line and a second conductive line disposed in a first dielectric layer. The height of the first conductive line is greater than a height of the second conductive line. The semiconductor structure further includes a first via layer having a second dielectric layer disposed on a top surface of the first metallization layer and a first via in the second dielectric layer. The first via is configured to expose a portion of a top surface of the second conductive line. The semiconductor structure further includes a first conductive material disposed in the first via.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.