Well-controlled edge-to-edge spacing between adjacent interconnects

US11195795B1 · kind B1 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Brent A. Anderson · Jericho, US
• Lawrence A. Clevenger · Saratoga Springs, US
• Nicholas Anthony Lanzillo · Wynantskill, US
• Christopher J. Penny · Saratoga Springs, US
• Kisik Choi · Hopewell Junction, US
• Robert R. Robison · Colchester, US

Key dates

• Filing date: Jun 3, 2020
• Grant date: Dec 7, 2021
• Expiry date: Jun 3, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L23/5226
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.